By alternately loading the 2′s complement of DATUM and making the pin high followed by DATUM itself making the pin low will give us a total period approximately the same as a total Timer 0 time-out as if counting through all 256 states. Conversely loading in the value of DATUM will give a time-out duration inversely proportional to the value. If we load in the the 2′s complement of the byte (the negative value) then the duration will be proportional to this value – the larger it is the longer the timer has to count before overflowing. Timer 0 will give a time-out related to a number loaded into the timer at the beginning of the period. Assuming an 8 MHz crystal, calculate the PWM duration. Show how you could use Timer 0 to generate a PWM version of a digital byte in file register DATUM using pin RA0 as the output. If a second CCP module is used, an extra PWM output at pin RC1/CCP2 is available with a separate duty cycle but an identical period, as Timer 2 is a shared resource. The Timer 2 postscaler does not affect the PWM generation but still sets the TMR2IF in the normal way. The programmer need only place the duty cycle datum in CCPR1L and CCP1CON (the latter can be left at its reset value of zero if the datum is to be treated as 8-bit) and a PWM signal will automatically be generated with no software overhead. Reducing the value in PR2 would also increase the repetition frequency. A prescale ratio of 1:1 would increase the period frequency to 19.53 kHz. In this case the PWM frequency is ^ x jg x 256 = 1.22 kHz. For example, if PR2 = 3Fh then the resolution is reduced to eight bits – six in PR2 and two in the prescaler.įor our example let us assume a crystal frequency of 20MHz, a prescale ratio of 1:16 and a PR2 value of FFh. Smaller values of Timer 2 period data will reduce this resolution. If PR2 is FFh then the resolution of the system is a full ten bits. In all cases the datum in CCPR1L must be smaller than that in PR2, otherwise the PWM latch will never reset! 4.4.This gives a period resolution equal to the crystal period. Where the Timer 2 prescale is set to 1:1 the lower two bits used on the timer side are the quadrature clock phases described in Fig. The RC2/CCP1 pin direction should be set to output.The duty cycle datum can be glitchlessly changed by the software at any time by updating the slave registers and will take effect in the PWM period following this update.The duty cycle is set by the 10-bit datum in CCPR1L:CCP1CON.The PWM period is set by the Timer 2/PR2 time-out.The PWM latch is set, CCP1 goes high and the 10-bit slave duty cycle register/latch us updated. The next clock pulse after Timer2 reaches the datum in PR2 it is reset. When Timer 2:Prescaler equals DC1B the PWM latch resets and pin CCP1 goes low.ģ. Thus we have the following sequence of operations repeated indefinitely:Ģ. CCPR1H is not directly writable to in this mode. This datum is loaded into the CCPR1H and a slave 2-bit latch each time Timer 2 rolls over. Taken together this gives a 10-bit duty-cycle datum DC1B. This gives the PWM repeat period.Ī second CCP equality comparator matches the 10-bit duty cycle number which is set up by the program in CCPR1L and the two bits DC1B (Duty Cycle 1 Bits) in CCP1CON. When the Timer 2 comparator causes the count to reset, it also sets the PWM latch. Here Timer 2 runs with a period determined by the main crystal, prescaler and Period Register 2 as previously described. Thus if the duty cycle datum was 9Fh and the period count was module-256 (00-FFh) then the average power would be 62.5% (|).ĬCP modules have a PWM mode in conjunction with Timer 2, as shown in Fig. It is relatively easy to generate a PWM waveform solely in software by simply counting and setting a port pin when the count rolls over to zero and resetting the pin when it equals the datum representing the duty cycle.
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